This application is based on German priority application 19930225.1, which is hereby incorporated in its entirety by reference.
The present invention relates to phase lock loop synthesizer circuits, and more particularly to a PLL synthesizer circuit and a method for operating a PLL synthesizer circuit which improves the frequency change with regard to changing over into the frequency change operating mode and switching back into the receive operating mode.
The present invention relates to a method for operating a PLL synthesizer circuit, and to a PLL synthesizer circuit.
PLL synthesizer circuits are well known from the prior art. The principle of such a circuit may be explained with reference to FIG. 3. Starting from the fixed reference frequency of a local oscillator (quartz) 1, selectable output frequencies are to be provided at a voltage-controlled oscillator (VCO) 10. For this purpose, the reference signal of the local oscillator 1 is fed to a programmable reference divider 2, and the divided reference signal is then conducted to a phase detector 3. The phase detector 3 outputs an output signal proportional to the detected difference between the phase of the divided reference signal and the phase of a signal fed from a programmable divider 12. The output signal of the phase detector 3 is low-pass filtered (loop filter 21), and the low-pass filtered voltage signal is then fed to the VCO 10. The output signal of the VCO 10 is, on the one hand, derived as the desired signal and, on the other hand, fed to the phase detector 3 and via a further programmable divider 12. The divider values of the programmable dividers 2 and 12 can be driven by a microprocessor 14.
The divider values of the programmable dividers 2 and 12 are changed by varying the control value of the microprocessor 14. After each frequency change, the control loop must then resettle and finally lock. This settling time constant is codetermined, for example, by the delay time (time constant) of the low-pass loop filter 21. It may be stated as a rule of thumb that the settling time of the closed loop for xe2x80x9clockingxe2x80x9d onto a new frequency lasts approximately 100 periods of the divided reference frequency fed to the phase detector 3. This works out to, for example, 0.1 s in the case of a frequency of 1 kHz.
However, in the case of receiving systems with PLL synthesizers it is important, inter alia, to carry out the frequency change as quickly as possible and at the same time to achieve as large as possible a signal-to-noise ratio (S/N) in the receive state, that is to say in the case of a fixed frequency. Both conditions, specifically a quick frequency change and large signal-to-noise ratio cannot normally be achieved with the aid of a single loop filter or, to put it generally, with the aid of a single time constant of the PLL loop. It is therefore known to provide low-pass loop filters with different time constants, for example by using a switching unit to select low pass filters with different time constants in a parallel-connected fashion. A problem in this case is that each change of the time constant can then be heard in the audio receiving system, since equipotential bonding takes place during switching over. Because of the smaller time constant, the time advantage gained is then generally nullified again by mute measures which necessarily follow.
U.S. Pat. No. 5,420,545 exhibits a frequency synthesizer which includes in the feedback path a programmable divider whose divider factor can be varied via a control circuit as a function of the desired output frequency. Moreover, in the case of frequency change the bandwidth of the loop filter is increased in order to permit a quicker settling to the new frequency. The control device is caused to do this by a frequency change signal. EP-A2-0 669 722 exhibits a similar phase-locked loop in which the time constant of the loop filter is varied in the case of a change in the frequency divider ratio. The loop filter includes a circuit with a variable resistor. The time constant of the loop filter is reduced so that locking of the PLL after a frequency change is accelerated. In the case of another phase-lock loop exhibited in EP-A2-0 211 594, two loop filters are provided which are switched selectively as a function of a change in the frequency divider ratio.
EP-A1-0 582 390 exhibits a phase-locked loop in which a changeover is made between two different loop filters as a function of the phase error provided by the phase comparator. In the case of a low phase error, the loop filter with a small bandwidth is activated, and in the case of a larger phase error the loop filter with a large bandwidth is activated.
Further possibilities are known for accelerating the frequency change. Thus, for example, the current of the charge pump in the PLL loop can be markedly increased, or the loop amplifier can be operated with a larger current.
Because of the problem, addressed above, of equipotential bonding during the switchover of time constants in the case of the loop filter, the prior art is frequently restricted to only increasing the current of the charge pumps for the frequency change operation. This is impossible without noise in the settled state of the PLL. Consequently, the circuit is mostly optimized such that in the case of the maximum achievable S/N the settling time achieved is simply accepted, and further optimization is possible only to the detriment of the S/N.
It is an object of the present invention to provide a technique for PLL synthesizers which improves the frequency change with regard to the changeover into the frequency change operating mode and the switching back into the receive operating mode.
Thus, according to the invention a method is proposed for operating a PLL synthesizer circuit. As is known from the prior art, the output frequency of the PLL synthesizer circuit can be selected by appropriately driving a programmable divider circuit in a feedback loop of the PLL synthesizer circuit. The PLL synthesizer circuit of the present invention can be operated in a receive operating mode (fixed frequency) and at least one further operating mode (frequency change mode). In the frequency change mode, the PLL synthesizer circuit has a settling time constant which is reduced by comparison with that of the receive operating mode, with the result that the frequency change can be performed comparatively swiftly. The PLL synthesizer circuit is changed over in this case into the frequency change mode (that is to say that frequency change operating mode with a small settling time constant) as a function of a detection that the programmable divider circuit is being driven with a changed value. If, specifically, a frequency change is carried out by appropriately driving the programmable divider circuit, the closed loop is taken out of its settled state, and the phase difference grows without restriction, as it were. In this state, reception is impossible in any event, with the result that it is also possible, for example, to reduce the time constant of the low-pass filter, since it is not necessary to place any value on a large signal-to-noise ratio in the case of the frequency change. It is then possible to switch back into the receive operating mode as soon as the phase difference between the output signal of the programmable divider circuit and a reference frequency undershoots a prescribed threshold value. Thus, switching back into the receive operating mode is started at a different point in the PLL loop than is the triggering of the frequency change mode.
The changeover into the frequency change operating mode is not triggered in the present invention by detecting the overshooting of a predetermined limiting value by the phase difference. Specifically, the phase difference can also overshoot the predetermined limiting value without an undesired frequency change owing to disturbing influences on the PLL loop. The result in this case would be to initiate the frequency change mode unnecessarily. The frequency change mode is initiated in the present invention only when the aim is actually to carry out a frequency change by appropriate driving of the programmable divider.
If the change into the frequency change mode has been initiated, at least one of the following can be executed:
the current of a charge pump of the PLL synthesizer circuit can be increased,
the current of a loop amplifier of the PLL synthesizer circuit can be increased,
the time constant of a loop filter of the PLL synthesizer circuit can be reduced, and/or
the programmable divider circuit and a programmable reference divider circuit between a reference oscillator and a phase detector of the PLL synthesizer circuit can each be driven to a higher frequency, as a result of which the phase detector is fed signals of raised frequency.
As mentioned above, the settling time of the PLL loop up to locking depends, inter alia, on the frequencies fed to the phase detector. It is therefore possible to reduce the settling time by increasing these frequencies.
According to the invention, a PLL synthesizer circuit is further provided. This PLL synthesizer circuit has a programmable divider circuit which is driven by a controller for the purpose of selecting a desired output frequency of the PLL synthesizer circuit. An operating mode selector circuit optionally drives a receive operating mode and at least one further operating mode (frequency change operating mode) of the PLL synthesizer circuit, the PLL synthesizer circuit having in the frequency change operating mode a settling time constant which is reduced by comparison with the receive operating mode.
Means are provided for detecting the driving of the programmable divider circuit by the controller with the aid of a changed driver value, which means output a detection signal to the operating mode selector circuit, which signal causes the latter to drive the frequency change operating mode.
A phase detector and an interlocking detector are provided, in which case the interlocking detector compares the output signal of the phase detector with a threshold value, and in the case when the output signal of the phase detector undershoots the threshold value, outputs an interlocking signal to the operating mode selector circuit which causes the latter to drive the receive operating mode.
In order to reduce the settling time constant of the PLL synthesizer circuit in the frequency change operating mode, it is possible to provide a charge pump whose current can be increased in the frequency change operating mode.
Alternatively or in addition, the current with which a loop amplifier is operated can be increased in the frequency change operating mode.
Alternatively or in addition, a loop filter with a selectable time constant can be provided, with the time constant being reduced in the frequency change operating mode.
Alternatively or in addition, in order to reduce the settling time constant of the PLL synthesizer circuit in the frequency change operating mode, it is possible to provide a programmable reference divider circuit between a reference oscillator and a phase detector of the PLL synthesizer circuit which is driven in each case to a higher frequency in the frequency change operating mode by the operating mode selector circuit together with the programmable divider circuit.
It is possible to provide two parallel loop filters with different time constants, a switch selecting the loop filter with the larger time constant in the receive mode.
A high-resistance resistor can be connected between the two loop filters for the purpose of equipotential bonding. It is possible in this way to avoid the problem of xe2x80x9cclickingxe2x80x9d, that is to say the audible equipotential bonding in the case of audio receiving systems.
Alternatively, for the purpose of changing the time constant of a loop filter it is possible to connect a resistor in parallel with a loop filter by means of a switching unit. Consequently, in this case the switching unit is not a changeover switchxe2x80x94rather, the parallel-connected resistor is only switched on or off. In this case, as well, the problem of; equipotential bonding which can lead to an audible clicking noise is eliminated.